SOC Physical Design, Static Timing Analysis Engineer

Intel Corporation

Physical Design Timing Engineer at Intel involved in shaping performance and power efficiency of SoC designs. Collaborating across teams for innovative solutions in high-performance technology.

Posted 4/28/2026full-timePhoenix • Arizona, California • 🇺🇸 United StatesSeniorLead💰 $164,470 - $311,890 per yearWebsite

About the role

Key responsibilities & impact

Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
Define methodologies to produce high-quality timing models and enable efficient physical design execution.
Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Requirements

What you’ll need

Bachelor's degree with 8 +years or master’s degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field
7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
3+ years of experience with the following skills: Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
Familiarity with TCL scripting and timing budgeting processes.

Benefits

Comp & perks

competitive pay
stock bonuses
health
retirement
vacation

ATS Keywords

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Hard Skills & Tools

SOC level timing analysistiming optimizationtiming constraintstiming violationstiming rollupsclock network designtiming closure methodologiestiming constraint adaptationphysical design knowledgeoptimization techniques