Understand design dataflow and chip-level floor-planning constraints to set up partition floorplans with macro/pin placements and keep-outs.
Work with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR and DRC violations.
Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets.
Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.

Requirements

Bachelors & 4+ years or Masters & 3+ years or PhD with hands-on physical design experience.
3+ year of experience in synthesis, place and route and timing/layout closure.
3+ years of experience with scripting languages such as Perl, TCL, Python, etc.

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

physical designsynthesisplace and routetiming closurelayout closureVCSSDF simulationscustom scriptinglow power designhigh performance design

Certifications

Bachelor's degreeMaster's degreePhD