Senior Formal Verification Engineer – AI SoC Development
Intel Corporation
full-time
Posted on:
Location Type: Hybrid
Location: Folsom • California, Oregon • 🇺🇸 United States
Visit company websiteSalary
💰 $214,730 - $303,140 per year
Job Level
Senior
Tech Stack
PerlPython
About the role
- Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
- Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
- Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
- Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
- Drive formal sign-off, including convergence analysis and coverage closure.
- Contribute to pre-silicon verification, chip bring-up, and post-silicon debug support.
- Mentor junior engineers and establish best practices for formal verification methodology.
- Define and develop scalable, reusable verification plans for block, subsystem, and SoC levels.
- Execute verification plans and run emulation and system simulation models to validate design, analyze power/performance, and uncover bugs.
- Debug and root-cause issues in the presilicon environment; implement corrective measures.
- Collaborate with architects, RTL developers, and physical design teams to improve verification of complex features.
- Document test plans and lead technical reviews with design and architecture teams.
- Incorporate and execute security verification activities within regression and debug tests.
- Maintain and enhance existing functional verification infrastructure and methodology.
- Apply learnings from post-silicon validation to improve coverage and quality for future products.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of related experience.
- 7+ years of experience in ASIC/SoC verification with at least 3+ years focused on formal verification.
- Expertise in formal verification methodologies and tools (e.g., JasperGold, VC Formal, Questa Formal).
- Strong knowledge of System Verilog Assertions (SVA) and property-based verification.
- Deep understanding of digital design concepts, clock domain crossings, and low-power design techniques.
- Familiarity with UVM-based simulation environments and how formal complements dynamic verification.
- Scripting skills (Python, TCL, Perl) for automation and flow optimization.
- Ability to lead projects, work cross-functionally, and deliver under tight schedules.
- Strong analytical skills, attention to detail, and a collaborative mindset.
Benefits
- competitive pay
- stock
- bonuses
- health
- retirement
- vacation
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
formal verificationSystemVerilog Assertions (SVA)formal propertiesverification plansemulationsystem simulationdebuggingscripting (Python, TCL, Perl)low-power design techniquesUVM-based simulation
Soft skills
mentoringcollaborationanalytical skillsattention to detailproject leadershipcross-functional teamworkdelivery under tight schedules