DFT Design Engineer
Intel Corporation
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California, Oregon, Texas • 🇺🇸 United States
Visit company websiteSalary
💰 $139,710 - $262,680 per year
Job Level
Mid-LevelSenior
About the role
- Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support
- Generates test content and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN)
- Collaborates in the definition of architecture and microarchitecture features
- Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE)
- Optimizes logic to meet power, performance, area, timing, and test coverage goals
- Ensures design features are verified correctly and resolves issues
- Integrates DFT blocks into functional IP and SoC
- Collaborates with post silicon and manufacturing team to verify feature on silicon
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience — or — Master’s degree in the same fields with 3+ years of relevant experience — or — PhD in the same fields with 6+ months of relevant experience
- Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification
- Expertise in Tessent DFT tool
- Expertise in Primetime especially in DFT constraints
- Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT
Benefits
- competitive pay
- stock
- bonuses
- health
- retirement
- vacation
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL codingDFT timing closuretest content generationHVM content developmentlogic optimizationDFT integrationDFT Array TestDFT Verificationquality checkstiming analysis
Soft skills
collaborationproblem-solvingissue resolution