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Mixed Signal Design Verification Engineer
Intel CorporationMixed-signal verification engineer validating Intel silicon logic and power-delivery designs. Developing simulation environments, debugging presilicon issues, and collaborating across architecture and design teams.
Posted 9/4/2026full-timeHillsboro • Oregon, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $122,440 - $200,340 per yearWebsite
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in functional verification of mixed signal logic components, including analog behavioral modeling and the development of IP verification plans. Proficient in VHDL, Verilog, and SystemVerilog, with strong skills in testbench development and design debugging.
Highest-signal resume keywords
Functional VerificationVHDL/Verilog/SystemVerilogTestbench DevelopmentDesign DebuggingAnalog Debug Skills
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Mixed Signal Logic ComponentsAnalog Behavioral ModelingIP Verification PlansSystem Simulation ModelsPower AnalysisTiming AnalysisRoot-Cause AnalysisCorrective Measures ImplementationDigital Logic ExperienceReal Number Simulation Modeling
Soft Skills
CollaborationTechnical Review Leadership
Tools & Technologies
OVMUVM
Industry Keywords
Electrical EngineeringComputer EngineeringComputer SciencePresilicon EnvironmentMicroarchitecture Specifications
About the role
Key responsibilities & impact- Perform functional verification of mixed signal logic components, including analog behavioral modeling
- Develop IP verification plans, test benches, and verification environments for mixed signal microarchitecture specifications
- Execute verification plans and define and run system simulation models to verify designs, analyze power and timing, and uncover bugs
- Replicate, root-cause, and debug issues in the presilicon environment
- Implement corrective measures to resolve failing tests
- Collaborate with digital and analog architects, RTL developers, and physical design teams
- Improve verification of complex architectural and microarchitectural features and meet functional, performance, and power goals
- Document test plans and drive technical reviews with design and architecture teams
- Maintain and improve functional verification infrastructure and methodology
Requirements
What you’ll need- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience, or Master's Degree in those fields with 2+ years of experience
- Digital logic experience
- VHDL/Verilog/SystemVerilog experience
- Testbench component development, preferably in OVM/UVM
- Design debugging skills
- Relevant experience may be obtained through schoolwork, classes, project work, internships, military training, and/or work experience
- Preferred: 7+ years of related experience
- Preferred: Analog debug skills
- Preferred: Real number (current, voltage) simulation modeling and debug skills
Benefits
Comp & perks- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation benefits
- Hybrid work model allowing employees to split time between on-site and off-site work