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ASIC Front-end Design Engineer
Hewlett Packard EnterpriseASIC Design Engineer responsible for defining high-performance blocks and collaborating across teams on advanced networking ASICs. Join HPE to innovate in data management.
About the role
Key responsibilities & impact- Define and architect high-performance blocks for the latest, most advanced networking ASICs
- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
- Collaborate with the verification team in the development of the testplan and assist in debugging test failures
- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Requirements
What you’ll need- Strong Verilog RTL coding skills
- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
- Knowledge of high performance memory subsystems
- Knowledge of multi-domain clock synchronization and high-speed serial interfaces
- Strong problem solving and ASIC debugging skills
- Excellent written and verbal communications skills
- MSEE or BSEE is required
Benefits
Comp & perks- Health & Wellbeing
- Personal & Professional Development
- Unconditional Inclusion
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
VerilogRTL codingASIC designmicro-architecturelogic designtiming analysistiming fixeshigh performance memory subsystemsmulti-domain clock synchronizationhigh-speed serial interfaces
Soft Skills
problem solvingdebugging skillswritten communicationverbal communication
Certifications
MSEEBSEE