Mechanical Engineer

• Responsible for the pre-silicon verification of IP modules, IP subsystems, and/or SoC top.
• Responsible for defining digital verification strategy and plan for SoC top or its sub-modules.
• Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP subsystem, SoC system.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for developing, debugging and running C/C++, System Verilog or UVM based verification environment for RTL/netlist simulation.
• Define and develop test cases in an appropriate verification framework.
• Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyse.

Design Engineer – Verification

Senior Battery System Design Engineer

Design Engineer – Electrical

GSE Design Engineer – Mechatronics & Automation