ASIC Physical Design Engineer

Fortive

ASIC Physical Design Engineer implementing SOC devices at Tektronix. Collaborating with cross-functional teams in Louisville, CO or Beaverton, OR to deliver industry-leading solutions.

Posted 7/30/2026full-timeBoulder • Colorado, Oregon • 🇺🇸 United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC digital physical design implementation, including RTL to GDSII processes, static timing analysis, and physical signoff activities. Proficient in scripting and automation to enhance design methodologies and collaboration across engineering teams.

Highest-signal resume keywords

ASIC Physical Design ImplementationStatic Timing AnalysisPhysical Signoff ChecksScripting and Automation SkillsIndustry-Standard EDA Tools

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC DesignFloorplanningPlace-and-RouteClock Tree SynthesisRoutingTiming ClosureDRCLVSIR Drop AnalysisElectromigration

Tools & Technologies

CadenceSynopsysSiemens EDATclPythonPerlShell Scripting

Industry Keywords

RTLGDSIISoCTiming ConstraintsMulti-Mode VerificationCongestion ResolutionSignal IntegrityECO Practices

Tech Stack

Tools & technologies

PerlPythonShell Scripting

About the role

Key responsibilities & impact

Execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII, including floor-planning, placement, clock tree synthesis, routing, and design closure.
Drive place-and-route execution using industry-standard EDA tools, optimizing designs for timing, power, area, signal integrity, and routability.
Perform static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues to achieve timing closure.
Support physical signoff activities, including DRC, LVS, formal equivalence checking, extraction, IR drop, electromigration, and signal integrity analysis.
Collaborate with RTL design, verification, DFT, analog, packaging, and product architecture teams to resolve implementation issues and ensure a timing-closed, manufacturable, tapeout-ready design.
Develop and maintain scripts, flows, documentation, and review materials that improve physical design methodology, automation, quality, and schedule predictability.

Requirements

What you’ll need

BS in Electrical Engineering or equivalent experience.
5+ years of hands-on experience ASIC physical design from RTL to verified GDS.
Hands-on experience with ASIC or SoC physical design implementation, including floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure.
Working knowledge of RTL-to-GDSII physical design flows and the ability to resolve implementation issues related to congestion, timing, power, area, and signal integrity.
Experience with static timing analysis, timing constraints, multi-mode multi-corner timing verification, and timing closure at the block or SoC level.
Familiarity with physical signoff checks and related debug activities, including DRC, LVS, extraction, formal equivalence checking, IR drop, electromigration, and crosstalk analysis.
Proficiency with industry-standard physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA.
Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting to support physical design flows, debug, reporting, and methodology improvement.
Provide feedback to RTL and packaging design teams to improve design hand-off quality and standard work processes.
Basic knowledge of industry standard ECO practices.

Benefits

Comp & perks

Health insurance
401(k) matching
Flexible work hours
Paid time off
Remote work options