VLSI Verification Engineer

Expert Executive Recruiters (EER Global)

VLSI Engineer specializing in ASIC/SoC verification for high-performance AI accelerator products. Collaborating with multidisciplinary teams on cutting-edge hardware in a rapidly growing deep-tech environment.

Posted 7/24/2026full-timeGdańsk • 🇵🇱 PolandMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC/SoC verification, including the development of UVM-based verification environments and the implementation of constrained-random verification methodologies. Proficient in debugging complex hardware and software interactions while collaborating effectively with multidisciplinary teams.

Highest-signal resume keywords

ASIC/SoC VerificationSystemVerilogUVMConstrained-Random VerificationEDA Simulation Tools

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design PrinciplesRTL CodingVerilogVHDLDebugging Complex Digital LogicFunctional Coverage AnalysisHigh-Speed InterfacesMemory SubsystemsAI/ML AcceleratorsBuilding UVM Environments

Soft Skills

Analytical MindsetCommunication SkillsCollaboration

Tools & Technologies

Synopsys ToolsCadence ToolsSiemens/Mentor Tools

Industry Keywords

Verification PlansRTL SpecificationsSubsystem IntegrationSoC-Level VerificationProtocolsAXIPCIeDDRCXL

About the role

Key responsibilities & impact

Develop and execute verification plans based on architecture and RTL specifications.
Build, extend, and maintain UVM‑based verification environments, including agents, drivers, sequencers, monitors, scoreboards, and checkers.
Implement constrained‑random and coverage‑driven verification methodologies.
Debug complex hardware and hardware/software interactions using industry‑standard tools.
Collaborate with RTL designers, architects, and validation teams to identify issues and drive them to closure.
Analyze functional coverage, identify gaps, and ensure verification completeness.
Participate in subsystem and SoC‑level integration and verification activities.

Requirements

What you’ll need

B.Sc . or M.Sc . in Electrical Engineering, Computer Engineering, or a related field.
Minimum 5 years of hands‑on experience in ASIC/SoC verification.
Strong proficiency in SystemVerilog , UVM , and constrained‑random verification.
Solid understanding of digital design principles and RTL coding (Verilog/VHDL).
Experience with EDA simulation and debug tools from Synopsys, Cadence, or Siemens/Mentor.
Proven ability to debug complex digital logic and HW/SW interactions.
Strong analytical mindset, communication skills, and ability to work in multidisciplinary teams.
Experience with high‑speed interfaces, memory subsystems, or AI/ML accelerators (preferred).
Familiarity with protocols such as AXI, PCIe, DDR, or CXL (preferred).
Experience building UVM environments from scratch (preferred).

Benefits

Comp & perks

Equity participation with long‑term upside potential.
Full‑time employment contract.
Work alongside top global experts in a highly specialized domain not commonly found in Poland.
Opportunity to join a fast‑growing deep‑tech company building unique AI hardware products.
Competitive compensation and long‑term career growth within a stable, well‑funded organization.