Ethernovia

Senior ASIC Design Verification Engineer

Ethernovia

full-time

Posted on:

Location Type: Remote

Location: Canada

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Job Level

Senior

Tech Stack

Python

About the role

  • As a Senior ASIC Design Verification Engineer, you will be responsible for all aspects of digital SoC verification.
  • You will work with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems.
  • You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics.

Requirements

  • BS and/or MS in Electrical Engineering, Computer Science, or related field
  • Minimum 10+ years of ASIC verification experience
  • Strong understanding of ASIC verification fundamentals and industry standard methodologies
  • Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
  • Experience with the full verification flow, from spec to coverage analysis to gate level sim
  • Debugging failures in simulation to root cause problems
  • Self-motivated and able to work effectively both independently and in a team
Benefits
  • Pre IPO stock options
  • Competitive base salary
  • Flexible hours
  • Medical, dental and vision insurance for employees
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
ASIC verificationVerilogSystem VerilogUVMPythonTCLCC++verification flowcoverage analysis
Soft Skills
self-motivatedteamworkintegritywork ethicscommunicationcollaborationproblem-solvingtrustcohesivenessindependence
Certifications
BS in Electrical EngineeringMS in Electrical EngineeringBS in Computer ScienceMS in Computer Science