Staff DFT Engineer

EnCharge AI

Staff-level DFT Engineer joining EnCharge AI’s silicon team. Driving end-to-end DFT insertion processes for next-generation AI accelerators.

Posted 6/30/2026full-timeBangalore • 🇮🇳 IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in DFT architecture implementation, including advanced techniques for Edge AI architectures and high-coverage test pattern generation. Proven ability to collaborate with synthesis and STA teams while managing DFT constraints and debugging on silicon.

Highest-signal resume keywords

DFT Architecture ImplementationHigh-Coverage Test Pattern GenerationExpertise in Siemens TessentPower-Aware DFTLead Capacity in Tape-Out Cycle

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFTStatic Timing AnalysisHigh-Bandwidth Memory TestingLow-Power Test ModesHierarchical DFT FlowsTest Pattern VerificationBoundary ScanMBISTScanTransition Testing

Soft Skills

Problem-SolvingAdaptabilityCollaboration

Tools & Technologies

Siemens TessentSynopsys DFTMAXSynopsys TetraMAXCadence GenusCadence ModusAutomated Test Equipment

Industry Keywords

AI SOCsDFT-Centric STAYield ImprovementEdge AI ArchitecturesHigh-Speed IO Testing

About the role

Key responsibilities & impact

Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.
Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.
Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.
Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.
Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.
Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.

Requirements

What you’ll need

9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.
Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).
Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.
You are comfortable wearing multiple hats. You don't wait for a manual; you build the manual.
A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.

Benefits

Comp & perks

High Impact: In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.
Growth: You’ll be working alongside veterans from top-tier chipmakers, solving problems that haven't been solved yet.
Ownership: We value "intrapreneurs"—engineers who treat the product like it’s their own.