Efficient Computer

Mechanical Engineer

• Own feature development from specification through RTL design, implementation, and synthesis.
• Implement product features targeting both silicon and FPGA platforms.
• Develop robust unit testbench infrastructure and contribute to verification strategies.
• Design memory subsystems and integrate memory macros (SRAM, MRAM, etc.).
• Integrate and interface vendor-provided IP with custom RTL designs.
• Use industry-standard EDA tools across the full digital design flow (Cadence, Synopsys, Siemens/Mentor, ANSYS).
• Collaborate with physical design to resolve RTL issues and ensure high-quality tape-out.
• Partner with verification, software, and compiler teams to implement features that cross the hardware–software boundary, including support for Efficient’s dataflow ISA.
• Produce high-quality design documentation and participate in design reviews.
• Provide mentorship to junior engineers and contribute to best-practice development processes.

Senior Digital Design Engineer

• Lead physical design team from synthesis to sign-off and tape-out
• Run physical design tasks including synthesis and place-and-route
• Work with digital design team to integrate analog and digital IP into design
• Interact with design verification team and run verification tasks on design
• Resolve DRC & LVS violations to produce DRC-clean GDS-II of chip to deliver to foundry
• Interact with foundry partners through multi-party wafer and manufacturing runs
• Interact with backend services partners on physical design tasks through sign-off
• Implement and execute physical design management process with PD team
• Setup and maintain physical design tools, primarily Synopsys, but also potentially including Mentor/Siemens EDA, Cadence, or ANSYS tools as necessary
• Run power and energy modeling on synthesized, place-and-routed design
• Interact with digital design team to resolve RTL-level issues leading to DRC violations
• Mentor and train junior hardware physical design engineers

Lead Physical Design Engineer

• Design, implement, and verify features from specification through synthesis
• Measure, analyze, and optimize power consumption in digital designs from the front-end perspective, using industry-standard tools
• Implement product features at the RTL-level targeting silicon implementation
• Implement product features at the RTL-level targeting FPGA emulation for verification
• Build unit testbench infrastructure to verify implemented features
• Design of memory systems and digital integration of memory macros, including SRAM, MRAM, and others
• Interface design components with external/vendor-provided IP
• Use industrial-strength digital design tools from RTL simulation through synthesis, which may include Cadence, Synopsys, Mentor/Siemens EDA, and ANSYS as necessary
• Provide comprehensive feature and integration documentation
• Interact with physical design and digital verification team for pre-silicon verification
• Work with physical design team to resolve RTL-level issues leading to DRC violations
• Work with compiler and embedded software teams to develop, document, and implement features that span across the software-hardware boundary, including Efficient’s dataflow ISA