Staff Analog Design Engineer – Process Migration, Verification

d-Matrix

Staff Analog Design Engineer migrating SerDes and mixed-signal blocks for d-Matrix’s generative AI hardware. Building verification infrastructure and correlating silicon characterization with simulations.

Posted 8/18/2026full-timeSanta Clara • California • 🇺🇸 United StatesLead💰 $155,000 - $250,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in analog and mixed-signal circuit design, including migration between process nodes and verification methodologies. Proficient in building verification infrastructure and conducting silicon characterization with a focus on reliability and compliance.

Highest-signal resume keywords

Analog Circuit DesignMixed-Signal Verification MethodologyCadence VirtuosoPython ScriptingSilicon Characterization

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog Circuit DesignMixed-Signal Circuit DesignPost-Layout Back-Annotated SimulationBehavioral ModelingReliability AnalysisElectromigration ComplianceIR Drop AnalysisVerilog-A ModelingSerDes DesignMonte Carlo Simulation

Soft Skills

Problem SolvingCommunicationCollaboration

Tools & Technologies

Cadence VirtuosoSpectreADESKILLTCL

Industry Keywords

Process Node MigrationSilicon MeasurementsTestboard DesignD2D InterconnectATE Development

Tech Stack

Tools & technologies

Node.jsPython

About the role

Key responsibilities & impact

Lead migration of existing high-speed SerDes and mixed-signal blocks into new process nodes for the IO chiplet
Perform device mapping, re-sizing, bias/headroom re-budgeting, and re-verification against original specifications
Identify blocks whose architecture will not survive process-node changes and recommend solutions
Build and maintain analog verification infrastructure, including testbench frameworks, regressions, corner and Monte Carlo campaigns, and results management
Run post-layout back-annotated verification and resolve parasitic-driven issues with layout engineers
Generate and maintain behavioral and Verilog-A models correlated with transistor-level designs for full-chip verification
Own reliability and design-rule closure, including electromigration, IR drop, ESD/latch-up compliance, and aging
Contribute to testboard design and test-feature definition
Run silicon characterization by building bench setups, writing automation, and correlating measurements with simulations
Document characterization findings and feed them into design, future process-node migrations, product test, and reliability teams

Requirements

What you’ll need

BS or MS in Electrical Engineering
5+ years of hands-on analog or mixed-signal circuit design experience
Experience owning analog or mixed-signal blocks through working silicon, including bench characterization and lab debugging
Ability to explain ownership, silicon measurements, and how simulation-to-silicon gaps were closed
Direct experience migrating analog blocks between process nodes
Strong analog verification methodology, including corner and Monte Carlo strategy and post-layout back-annotated simulation
Fluency with Cadence Virtuoso, Spectre, and ADE
Scripting proficiency in Python, SKILL, TCL, or equivalent for verification and bench-measurement automation
Experience with 25 Gbps or higher per-lane SerDes preferred
FinFET or GAA circuit-design experience at 7nm or below preferred
Die-to-die interconnect experience such as UCIe, BoW, or proprietary D2D PHY preferred
Reliability-analysis flow experience preferred, including electromigration, IR drop, aging, and ESD verification
Verilog-A and behavioral-modeling experience, including model-to-silicon correlation, preferred
ATE and production-test development or IBIS-AMI model-generation experience preferred
Experience building durable verification or characterization infrastructure preferred
Legally authorized to work in the United States
Must disclose whether immigration-related employment-benefit sponsorship is required now or in the future

Benefits

Comp & perks

Equity
Bonus/incentive opportunities based on individual and company performance
Medical insurance
Dental insurance
Vision insurance
401(k)
Inclusive rewards plan focused on employee and loved ones’ wellbeing