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d-Matrix

Senior Signal Integrity Engineer

d-Matrix

Senior Staff Signal Integrity Engineer at d-Matrix focusing on electrical integrity of AI platforms. Leading modeling, simulation, and validation for high-speed interfaces and power delivery.

Posted 5/6/2026full-timeSanta Clara • California • 🇺🇸 United StatesSenior💰 $150,000 - $250,000 per yearWebsite

About the role

Key responsibilities & impact
  • Lead the end-to-end modeling, simulation, and correlation efforts—from the silicon die through the package and across the system PCBA.
  • Drive the SI/PI strategy for next-generation AI accelerators.
  • Lead the modeling and analysis of complex multi-chip packages.
  • Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements.
  • Perform comprehensive channel simulations using IBIS-AMI models.
  • Lead the "Gold Suite" validation in the lab.

Requirements

What you’ll need
  • MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity.
  • 12+ years in SI/PI design for high-performance networking, GPUs, or server platforms.
  • Expert-level proficiency in industry-standard tools: SI: Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor. PI: Ansys SIwave, Cadence PowerSI, or CST.
  • Proven track record with 112G SerDes and high-speed memory architectures. Deep understanding of PAM4 signaling and FEC (Forward Error Correction) impact on link margins.
  • Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes.

Benefits

Comp & perks
  • Medical/Dental/Vision
  • 401k
  • Diverse package of benefits centered around the wellbeing of our employees

ATS Keywords

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Hard Skills & Tools
modelingsimulationcorrelationPower Delivery Network (PDN)channel simulations112G SerDeshigh-speed memory architecturesPAM4 signalingForward Error Correction (FEC)electromagnetics
Soft Skills
leadershipstrategic planningproblem-solvingcollaborationcommunication