Ethernet ASIC Design Engineer
Cornelis Networks
TCP/IP
Senior ASIC Design Engineer
Cornelis Networks
full-time
Posted on:
Location Type: Remote
Location: Remote • California • 🇺🇸 United States
Visit company websiteJob Level
Senior
About the role
- Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development
- Develop microarchitecture specifications for Ethernet protocol blocks
- Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog
- Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage
- Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
- Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues
- Contribute to performance optimization and power-aware design strategies for Ethernet subsystems
Requirements
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
- 10+ years of industry experience in digital design with proficiency in Verilog and System Verilog
- Experience in RTL design for Ethernet protocols relevant to adapters and switches
- Familiarity with timing closure and modern physical design methodologies
- Proven ability in system-level debug and root cause analysis of technical issues
- Strong verbal and written communication skills
Benefits
- Equity, cash, and incentives
- Health and retirement benefits
- Generous paid holidays
- 401(k) with company match
- Open Time Off (OTO)
- Sick time
- Bonding leave
- Pregnancy disability leave
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
VerilogSystem VerilogRTL developmentEthernet protocolsPriority Flow ControlTCPUDPRoCEv2VLANECMP
Soft skills
communication skillscollaborationdebuggingroot cause analysis
