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Senior Principal ASIC Design Engineer
Cornelis Networks. Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
About the role
Key responsibilities & impact- Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
- Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
- Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
- Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
- Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.
Requirements
What you’ll need- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
- 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog
- Experience in RTL design for high-speed data paths or packet processing in ASICs
- Deep understanding of Host Ethernet adaptor architectures
- Familiarity with timing closure and modern physical design methodologies
- Proven ability in system-level debug and root cause analysis of technical issues
- Strong verbal and written communication skills.
Benefits
Comp & perks- Health insurance
- Retirement plans
- Paid time off
- Flexible work arrangements
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
VerilogSystem VerilogRTL designtiming constraintstiming closurepost-silicon validationperformance optimizationpower-aware designblock-level test planssystem-level test plans
Soft Skills
collaborationcommunicationdebuggingroot cause analysis
Certifications
B.S. degree in Computer EngineeringM.S. degree in Computer EngineeringB.S. degree in Electrical EngineeringM.S. degree in Electrical Engineering