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Senior ASIC Verification Engineer
Cornelis Networks. Responsible for verification closure of design modules or subsystems from test-planning to verification closure .
Tech Stack
Tools & technologiesSubversionTCP/IP
About the role
Key responsibilities & impact- Responsible for verification closure of design modules or subsystems from test-planning to verification closure
- Participate in ground-up development of UVM environments to verify RTL at block, unit, and SoC levels
- Develop and execute functional tests according to verification test plans
- Instrument testbench for functional and code coverage and drive to closure based on coverage metrics
- Collaborate with cross-functional teams like design, software, emulation, and silicon validation teams to ensure the highest design quality
Requirements
What you’ll need- 10 + years of experience in networking hardware verification
- Expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, UDP, TCP/IP, RDMA/RoCE, IPSec
- Proficient in System Verilog Language
- Experience with VCS or equivalent simulation tools
- Ground up testbench development and debugging using Verdi or equivalent tools
- Familiarity with Git or SVN
- B. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
- M. S. Degree in Computer Engineering, Computer Science, or Electrical Engineering (preferred)
Benefits
Comp & perks- Competitive compensation package including equity, cash, and incentives
- Health insurance (medical, dental, vision coverage)
- Retirement benefits (401(k) with company match)
- Paid holidays
- Open Time Off (OTO) for regular full-time exempt employees
- Sick time, bonding leave, and pregnancy disability leave
ATS Keywords
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Hard Skills & Tools
networking hardware verification50G Ethernet MAC/PCS protocols100G Ethernet MAC/PCS protocols400G Ethernet MAC/PCS protocolsUDPTCP/IPRDMA/RoCEIPSecSystem Verilogfunctional testing
Soft Skills
collaborationcross-functional teamwork