Senior Mechanical Engineer
Jacobs
React
ASIC Design Engineer
Cornelis Networks
full-time
Posted on:
Location Type: Remote
Location: Remote • 🇺🇸 United States
Visit company websiteJob Level
SeniorLead
About the role
- Implementation of the advanced ethernet protocols for the next generation ethernet ASICs.
- Write micro architecture specifications.
- Pre-silicon: Define timing constraints for the RTL block and work with Physical Design engineers for timing optimization.
- Pre-silicon: Work with the verification engineers to create block/system level test plans and ensure that the design is adequately covered.
- Post-silicon: Work with hardware/firmware/software engineers to resolve ASIC issues.
Requirements
- B.S. or M.S. degree in Computer or Electrical Engineering
- 10+ years of post-college experience in digital design with proficiency in Verilog, System Verilog
- Relevant experience in timing closure and familiarity with modern physical design methodologies
- Demonstrated strength with system level debug and determining root cause of technical issues
- Strong verbal and written communications skills.
Benefits
- Performance-based incentives, including an annual bonus or sales incentives
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
VerilogSystem Verilogdigital designtiming closuretiming constraintsmicro architecture specificationsblock/system level test planssystem level debugroot cause analysis
Soft skills
strong verbal communicationstrong written communication
Certifications
B.S. degree in Computer EngineeringM.S. degree in Electrical Engineering
