Senior Design Verification Engineer
Condor Computing Corporation
full-time
Posted on:
Location Type: Remote
Location: Texas • United States
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Job Level
About the role
- Architect and implement testbenches utilizing UVM-based methodologies
- Design and develop Verification Components using UVM-based techniques
- Conduct block-level verification to ensure optimal block performance and compliance with requirements
- Generate and execute verification plans based on specifications
- Define, implement, and analyze coverage metrics
- Architect and implement Formal Verification processes
- Create automation tools to streamline testing
- Perform testing for design performance evaluation
Requirements
- A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science
- 8+ years of experience in Verification
- Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception
- In-depth knowledge of event-driven simulator-based modeling techniques
- Experience with low-power implementation (UPF)
- Familiarity with scripting languages such as Python, Ruby, or Perl
- A comprehensive understanding of chip and/or computer architecture
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
UVMSystemVerilogtestbenchesverification componentsblock-level verificationcoverage metricsFormal Verificationautomation toolsevent-driven simulationlow-power implementation