ASIC DFT Engineer – 8+ years – DFT, ATPG, MBIST, SCAN, JTAG

Cisco

ASIC DFT Engineer developing innovative test features for Cisco's hardware solutions. Collaborating with teams for integration and validation of DFT in designs.

Posted 7/24/2026full-timeBangalore • 🇮🇳 IndiaSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Hardware Design-for-Test (DFT) implementation, including JTAG protocols, ATPG, and EDA tools. Proficient in post-silicon validation and debugging, with strong collaboration skills across multi-functional teams.

Highest-signal resume keywords

Hardware Design-For-Test (DFT)JTAG ProtocolsATPGEDA ToolsPost-Silicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT ImplementationScan InsertionGate Level SimulationDebugging with VCSScripting (Tcl, Python, Perl)

Soft Skills

Strong Verbal SkillsAbility to Thrive in Multifaceted Environment

Tools & Technologies

TestMaxTetramaxTessent Tool Sets

Industry Keywords

Silicon EngineeringATE PatternsP1687

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams.
Play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Craft solutions and debug with minimal mentorship.

Requirements

What you’ll need

Bachelor's or a Master’s Degree in Electrical or Computer Engineering
At least 8-10 years of experience
Knowledge of the latest innovative trends in DFT, test and silicon engineering
Experience with Jtag protocols, Scan insertion and ATPG
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets
Experience working with Gate level simulation, debugging with VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns, P1687
Strong verbal skills and ability to thrive in a multifaceted environment
Scripting skills: Tcl, Python/Perl

Benefits

Comp & perks

Health insurance
Retirement plans
Paid time off
Flexible work arrangements