ASIC Technical Leader – DFT

Cisco

ASIC Technical Leader at Cisco implementing Design-for-Test strategies for high-complexity ASICs in networking hardware. Collaborating with design teams to ensure quality and validation across various platforms.

Posted 7/24/2026full-timeRemote • California, Massachusetts, Texas, Washington • 🇺🇸 United StatesSenior💰 $210,600 - $305,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Hardware Design-for-Test (DFT) implementation, including JTAG protocols and BIST architectures, while collaborating with multi-functional teams for innovative DFT IP development and validation processes.

Highest-signal resume keywords

Hardware Design-For-Test (DFT)JTAG ProtocolsBIST ArchitecturesSystem Verilog Logic Equivalency CheckingATPG and EDA Tools

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Hardware Design-For-Test (DFT)JTAG ProtocolsBIST ArchitecturesSystem Verilog Logic Equivalency CheckingMemory BISTBoundary ScanPost Silicon DebugTest-Timing ValidationInnovative DFT IP DevelopmentReusable Test and Debug Strategies

Tools & Technologies

TestMaxTetramaxTessent Tool SetsPrimeTime

Industry Keywords

Silicon Device ModelsBare DieStacked DieIntegration and ValidationMulti-Functional Teams

About the role

Key responsibilities & impact

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die.
Driving re-usable test and debug strategies.

Requirements

What you’ll need

Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year
Exempt employees participate in Cisco’s flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
grants of Cisco restricted stock units