Physical Design Engineer

Cisco

Physical Design Engineer designing, developing, and testing advanced ASICs for Cisco’s core products. Working on performance, die size optimization, and best-in-class design methodologies.

Posted 7/18/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $123,600 - $174,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL-to-GDSII implementation, including synthesis, static timing analysis, and power integrity, while effectively collaborating with cross-functional teams and EDA vendors to optimize design methodologies.

Highest-signal resume keywords

RTL DesignStatic Timing AnalysisEDA Tools (Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre)Physical DesignPython Programming

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SynthesisHierarchical FloorplanningPlace and RouteTiming ClosurePower Integrity AnalysisTiming ECO ImplementationClock Tree Synthesis (CTS)Timing Constraints DefinitionTCL ProgrammingPerl Programming

Industry Keywords

Physical DesignDesign MethodologyMulti-ModeMulti-CornerTiming Methodologies

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

RTL-to-GDSII implementation, including synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks with a focus on performance and die size optimization
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements
Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology
Guide clock tree synthesis (CTS) strategies and provide actionable feedback to the implementation teams
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios
Complete Timing ECO implementation using Tweaker/Primetime-based flows and contribute to automation for STA methodology
Evaluate multiple timing methodologies/tools across different technologies and design types

Requirements

What you’ll need

Master's degree or Bachelor's degree in Electrical Engineering with work experience in Physical Design
Experience with RTL design and logic blocks
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre
Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
Experience with Python, TCL, or Perl programming

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
flexible vacation time off program
80 hours of sick time off provided on hire date
optional 10 paid days per full calendar year to volunteer