ASIC Design Hardware Engineer – SDC/STA

Cisco

Design/SDC Engineer contributing to next-generation networking chips at Cisco. Developing timing constraints and collaborating with teams to ensure seamless physical design closure.

Posted 7/17/2026full-timeSan Jose • California • 🇺🇸 United StatesMid-LevelSenior💰 $165,000 - $241,400 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in ASIC design and development, with a strong focus on timing constraints validation and digital design concepts. Proficient in HDL programming and scripting, contributing to the development of next-generation networking chips.

Highest-signal resume keywords

ASIC Design ExperienceTiming Constraints DevelopmentHDL Programming (Verilog/SystemVerilog)Scripting (TCL, Shell, Perl)Synthesis Tools (Synopsys DC/DCG/FC)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC DesignTiming Constraints ValidationDigital Design ConceptsBlock/Full Chip SDC DevelopmentMicroarchitectureRTL Implementation

Soft Skills

CollaborationGuidance

Tools & Technologies

TCMTimevisionPrimetimeSynthesis Tools

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringBachelor’s Degree in Computer EngineeringMaster’s Degree in Electrical EngineeringMaster’s Degree in Computer Engineering

Industry Keywords

Networking ChipsPhysical Design ClosureClocking DiagramsTiming ExceptionsAsync Boundaries

Tech Stack

Tools & technologies

Perl

About the role

Key responsibilities & impact

Work with exceptional talent with vast ASIC design and development expertise
Develop timing constraints at both block level and full-chip
Validate timing constraints using industry standard timing constraints verification tools such as TCM, Timevision
Collaborate with Front-end and Back-end teams to understand chip architecture
Guide teams in refining design and timing constraints for seamless physical design closure
Contribute to developing next-generation networking chips
Develop efficient methodology to promote block level SDCs to full-chip
Push down full-chip SDCs to block level
Review block level SDCs and clocking diagrams

Requirements

What you’ll need

Bachelor’s Degree in Electrical or Computer Engineering with 6+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 3+ years of ASIC or related experience
Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as Primetime and must have knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and must have strong experience scripting with TCL
Experience with digital design concepts (eg. clocking, timing exceptions and async boundaries)
Experience with block/full chip SDC development in functional and test modes
Experience with microarchitecture and RTL implementation

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter