ASIC Physical Design Lead

Cisco

ASIC Physical Design Technical Lead at Cisco working on fullchip floorplan and collaboration with design teams. Requires extensive experience in Physical Design and EDA tools for advanced technologies.

Posted 6/27/2026full-timeSan Jose • California, North Carolina, Texas • 🇺🇸 United StatesSenior💰 $183,800 - $263,600 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements
Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology
Proficiency in low-power design methodologies using UPF
Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams
Experience in using AI tools to improve productivity

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
Experience with custom clock (H-Tree or Mesh) at chip level
Experience with Python and usage of AI tools by giving accurate prompts

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year
accrued at rate of 4.92 hours per pay period for full-time employees
flexible vacation time off program
80 hours of sick time off provided on hire date
up to 80 hours of unused sick time carried forward from one calendar year to the next
additional paid time away may be requested for family emergencies
optional 10 paid days per full calendar year to volunteer
eligible to earn annual bonuses for non-sales roles
performance-based incentive pay for sales roles

ATS Keywords

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Hard Skills & Tools

Fullchip Floorplanhierarchical implementation flowstatic timing analysispower integrityphysical verificationlow-power design methodologiesRTL-to-GDSII implementationtiming closurecustom clock designPython

Soft Skills

collaborationproblem-solvinganalytical skillscommunication