Senior ASIC Physical Design Engineering Lead

Cisco

Senior ASIC Physical Design Engineering Technical Lead responsible for fullchip floorplanning and RTL-to-GDSII implementation at Cisco. Collaborating with design teams to optimize hardware solutions for AI technologies.

Posted 6/27/2026full-timeSan Jose • California, North Carolina, Texas • 🇺🇸 United StatesSenior💰 $210,600 - $305,100 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning.
Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
Proficiency in low-power design methodologies using UPF
Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams
Experience in using AI tools to improve productivity

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 12 + years of Physical Design experience or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience.
Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.
Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience with custom clock (H-Tree or Mesh) at chip level.
Experience with Python and usage of AI tools by giving accurate prompts.

Benefits

Comp & perks

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
flexible vacation time off program
80 hours of sick time off
option to volunteer 10 paid days per full calendar year

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Hard Skills & Tools

Fullchip Floorplanhierarchical implementation flowRTL-to-GDSII implementationstatic timing analysispower integritylow-power design methodologiestiming closurecustom clock designPythonAI tools

Certifications

Bachelor’s Degree in Electrical EngineeringMaster’s Degree in Electrical EngineeringPhD in Electrical Engineering