Principal Engineer, ASIC Physical Design

Cisco

Principal Engineer in ASIC Physical Design at Cisco, implementing RTL-to-GDSII flows for innovative hardware. Collaborating with global teams on Power, Performance, and Die-Size Optimization.

Posted 6/27/2026full-timeSan Jose • California, North Carolina, Texas • 🇺🇸 United StatesLead💰 $231,400 - $331,800 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

RTL-to-GDSII implementation, including Logic Synthesis, Hierarchical Floorplanning, Place and Route, Static Timing Analysis, Power Integrity, and Equivalence checks with a focus on Power, Performance and Die-Size Optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
Work closely with RTL, DFT, Implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.
Guide Clock Tree Synthesis (CTS) strategies and provide actionable feedback to the implementation teams.
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios.
Complete Functional and Timing ECO implementation using industry-standard flows and contribute to automation for STA methodology.
Evaluate multiple timing methodologies/tools across different technologies and design types.

Requirements

What you’ll need

Bachelor’s degree in Engineering and 15+ years of ASIC related experience, Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.
Experience developing and driving methodologies in the area of Power Optimization and Analysis.
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies.
Experience working with EDA tools like Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre.
Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis.
Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in Fullchip floor-planning and power grid planning.
Experience with custom clock (H-Tree or Mesh) at chip level.
Experience with Python, TCL, or Perl programming.

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
Flexible vacation time off program
80 hours of sick time off provided on hire date
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL-to-GDSII implementationLogic SynthesisHierarchical FloorplanningPlace and RouteStatic Timing AnalysisPower IntegrityEquivalence checksPower OptimizationTiming closureFullchip floor-planning