ASIC Engineering Technical Lead – DFT

Cisco

ASIC Engineering Technical Lead focused on Design-for-Test for optical communications products at Cisco. Leading DFT solutions implementation and testing processes for next-generation ASICs.

Posted 4/30/2026full-timeSan Jose • California, Massachusetts, Texas, Washington • 🇺🇸 United StatesSenior💰 $183,800 - $263,600 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Lead development of DFT solutions for next-generation ASICs for multi-100G to 1.6T coherent optical communications products
Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent, or Synopsys, tools for RTL and gate netlist DFT implementation
Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models
Drive scan-based diagnosis methodology for Silicon failure debug
Provide post-silicon testing and validation support
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Requirements

What you’ll need

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior experience working with ASICs
Prior experience in scan insertion and DFT setup, integration and validation
Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.
10+ years of experience working with ASICs (preferred)
10+ years of experience in scan insertion and DFT setup, integration and validation (preferred)
Experience driving ASIC DFT execution from concept through tapeout (preferred)
Experience working with ATE testers and test teams (preferred)
RTL experience to understand and debugging issues pertaining to DFT (preferred)
Ability to solve complex problems including clock domain crossings (preferred)
Familiar with advanced silicon process and technology nodes for high speed and low power consumption (preferred)
Strong implementation or integration of design blocks using Verilog/System Verilog (preferred)

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year for non-exempt employees
flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
additional paid time away for family emergencies
10 paid days per full calendar year to volunteer
annual bonuses for non-sales roles

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

DFT solutionsASICsscan insertioncompression logicdecompression logicmemory BISTlogic BISTATPG test pattern generationVerilogSystem Verilog

Soft Skills

problem solvingleadershipcommunication