Logic Design Engineer

Cisco

Logic Design Engineer responsible for chip design in Cisco's silicon development team. Writing RTL specifications and collaborating on full chip integration, validation and best practices.

Posted 4/26/2026full-timeCaesarea • 🇮🇱 IsraelMid-LevelSeniorWebsite

About the role

Key responsibilities & impact

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

Requirements

What you’ll need

B.Sc./M.Sc. in Electrical Engineering from a top university
6+ years of experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments

Benefits

Comp & perks

Health insurance
Flexible work arrangements
Professional development opportunities

ATS Keywords

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Hard Skills & Tools

RTLVerilogSystemVerilogtiming analysisperformance analysispower requirementsdebugroot-cause analysispost-silicon validationUVM

Soft Skills

collaborationproblem-solvingcommunication

Certifications

B.Sc. in Electrical EngineeringM.Sc. in Electrical Engineering