ASIC Design Verification Technical Leader

Cisco

Design Verification Lead driving ASIC design verification for silicon photonics at Cisco. Collaborating with teams to ensure high-performance networks and deployment of advanced optical solutions.

Posted 4/11/2026full-timeCarlsbad • California, Pennsylvania • 🇺🇸 United StatesSenior💰 $163,600 - $234,600 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Define and lead verification methodology and standards across multiple projects
Coordinate activities across multiple sites
Lead verification at block & chip level with various high-speed IPs integrated
Review specifications and participate in design reviews
Mentor and coach verification engineers
Debug complex silicon and system-level issues during bring-up phases
Support post-silicon bring-up and optimize integration and performance

Requirements

What you’ll need

Bachelor’s degree in Electrical or Computer engineering
8+ years of ASIC Design Verification experience, or
Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or
PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design Verification experience
Experience in System Verilog, UVM, and verification methodologies
Experience owning and delivering verification for large-scale SoCs or subsystems
Experience leading verification teams or projects
Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward from one year to the next
Optional 10 paid days per full calendar year to volunteer

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

ASIC Design VerificationSystem VerilogUVMscriptingautomationPythonPerlTCLShell Scriptsverification methodologies

Soft Skills

leadershipmentoringcoachingcoordinationdebuggingproblem-solvingcommunicationteam managementperformance optimizationdesign review participation

Certifications

Bachelor’s degree in Electrical EngineeringBachelor’s degree in Computer EngineeringMaster’s degree in Electrical EngineeringMaster’s degree in Computer EngineeringPhD in Electrical EngineeringPhD in Computer Engineering