DFT Engineer

Cirrus Logic

DFT Engineer working on industry leading mixed-signal SoCs for consumer audio markets. Taking part in test planning, insertion, and improvement of coverage.

Posted 6/17/2026full-timeAustin • Texas • 🇺🇸 United StatesJuniorMid-LevelWebsite

ATS Keywords

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Hard Skills

DFT featuresMemory BIST logicscan insertionATPG pattern generationtiming constraintsequivalence checkingMBIST verificationgate level simulationstest coverage analysistest cost planning

Soft Skills

collaborative teamwork

Tools & Technologies

FastScanTestKompressTetraMAXTest Compiler

Certifications & Qualifications

MSEEBS in relevant field

Industry Keywords

ASIC DFT designDFT verificationEDA tools

About the role

Key responsibilities & impact

Work within a collaborative team environment to define, implement, and review DFT features.
You will generate, insert, and verify Memory BIST logic.
Perform scan insertion and ATPG pattern generation.
Help develop and review DFT timing and equivalence checking constraints.
Perform MBIST and ATPG pattern verification with gate level simulations.
Identify and improve any test coverage gaps.
Perform test cost planning and analysis.
Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.

Requirements

What you’ll need

MSEE with 2+ years of experience or BS with relevant industry experience.
Possess strong hands on working knowledge on ASIC DFT design and verification.
Experience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc.

Benefits

Comp & perks

Cirrus Logic strives to select the best qualified applicant for any opening.
Different approaches, ideas and points of view are both valued and respected.
Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.