Physical Design Engineer
Cirrus Logic
full-time
Posted on:
Location Type: Hybrid
Location: Austin • Texas • United States
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About the role
- Responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout.
Requirements
- Master of Science in Electrical, Electronics, or Computer Engineering or a closely related field plus eight years of relevant experience.
- Alternatively, a Bachelor of Science in one of the foregoing fields plus ten years of relevant experience or a PhD in one of the foregoing fields plus six years of relevant experience is acceptable.
- Requires knowledge of RTL design and the ability to use synthesis tools, placement route implementation tools, static timing analysis tools, logic equivalence checking tools, power grid analysis tools, and design rule checking tools.
Benefits
- Cirrus Logic strives to select the best qualified applicant for any opening.
- Different approaches, ideas and points of view are both valued and respected.
- Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
RTL synthesistiming constraints creationPower analysischip floor planclock distributionfull chip assemblyTiming driven Placement & RouteStatic Timing Analysistiming closureECO