DFT Engineer
Cirrus Logic
full-time
Posted on:
Location Type: Hybrid
Location: Austin • United States
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About the role
- Work within a collaborative team environment to define, implement, and review DFT features.
- You will generate, insert, and verify Memory BIST logic.
- Perform scan insertion and ATPG pattern generation.
- Help develop and review DFT timing and equivalence checking constraints.
- Perform MBIST and ATPG pattern verification with gate level simulations.
- Identify and improve any test coverage gaps.
- Perform test cost planning and analysis.
- Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.
Requirements
- MSEE with 2+ years of experience or BS with relevant industry experience.
- Possess strong hands on working knowledge on ASIC DFT design and verification.
- Experience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc.
- Experience with Verilog, System Verilog, or VHDL.
- Understanding of low power test techniques and architectures.
- Knowledge of scripting languages such as Perl, Python, or TCL.
- Experience with synthesis, static timing analysis, and developing timing constraints.
- Strong oral and written communication skills.
- Experience with flows and automation.
- Work independently as well as part of a team.
- Have a curious and inquiring mind with the commitment to follow through on getting answers.
- Experience with debugging and root causing silicon problems.
Benefits
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Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
DFT designDFT verificationMemory BIST logicscan insertionATPG pattern generationtiming constraintssynthesisstatic timing analysisdebuggingroot causing
Soft Skills
communication skillsteam collaborationindependent workcuriositycommitment to follow through
Certifications
MSEEBS in relevant field