Chip Lead – Physical Design Director

Cadence Design Systems

Technical Lead for Physical Design at Cadence delivering SoC projects from RTL to GDS. Collaborating with customers to exceed Performance, Power, Area, and Schedule targets for advanced technology.

Posted 5/6/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesSeniorWebsite

Tech Stack

Tools & technologies

Node.jsPerlPython

About the role

Key responsibilities & impact

Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS.
Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements.
Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs.
Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency.
Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate.
Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements.
Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs

Requirements

What you’ll need

Fifteen or more years of industry experience in Physical Design.
Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
Demonstrated experience in complete design closure for chip top-level projects.
Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
Experience with advanced nodes at 7nm and below.
Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
Strong customer-facing communication and problem-solving skills.
Personal drive for continuous learning and expanding professional skill sets.
Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.

Benefits

Comp & perks

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Hard Skills & Tools

Physical DesignDesign for TestDigital Design FundamentalsStatic Timing AnalysisIC digital implementation flowsPlace and RouteClock Tree SynthesisIR Drop analysisPPA optimizationScripting languages

Soft Skills

customer-facing communicationproblem-solvingtechnical leadershipownership of technical decisionsinnovative problem solvingcollaborationdocumentationcontinuous learningbuilding technical relationshipspromoting initiatives