Physical Design Engineer
Broadcom
full-time
Posted on:
Location Type: Office
Location: San Jose • California • Colorado • United States
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Salary
💰 $127,100 - $226,000 per year
About the role
- Work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC)
- Drive tools and methodologies to achieve desired PPA metrics
- Complete equivalence checks, STA, Timing closure and power optimization
- Implement timing and functional ECOs
- Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon
Requirements
- BS in Electrical Engineering/ Computer Engineering or related field and 12+ years of related experience; or an MS in Electrical Engineering/ Computer Engineering or related field and 10+ years of related experience
- Primary expertise in place and route and/or timing (constraints, STA)
- Proficient in design implementation activities both at block and SoC level
- Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure
- Experience with formal verification, timing analysis and Eco implementation
- Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable
- Full chip tapeout experience based on 7nm and lower technologies is highly preferred
- Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
place and routetiming closurefloor-planningpartitioningplacementclock tree synthesistiming analysispower optimizationECO implementationformal verification