Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures
Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line
Analyze the interplay between design marginalities, voltage scaling, and manufacturing variations
Evaluate and implement cutting-edge AI-based EDA tools for root-cause analysis and systematic defect identification
Act as the "translator" between the Fab, Design, and Test teams, using data to prove where the silicon is diverging from the simulation

Requirements

Bachelor's degree plus 8+ years of related experience OR Master's degree plus 6+ years of related experience
3+ years in Silicon Debug, DFT, or Yield Engineering
Knowledge of Deep Sub-micron (FinFET) effects, including IR drop, crosstalk, and process variation
Experience with Pattern Recognition, Clustering (for defect binning), and Regression models
Expertise in Python, SQL, and big data environments (Spark, Snowflake, etc.)
Familiarity with industry-standard yield management systems (e.g., PDF Solutions, Synopsys YieldExplorer, or Cadence Clarity)

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

machine learningdata analysispattern recognitionclusteringregression modelsPythonSQLbig datadeep sub-micron effectsdesign-for-test

Soft Skills

communicationcollaborationproblem-solvinganalytical thinking