Lead the digital design and verification of analog mixed signal IP and IOs
Define the digital architecture and verification strategies for complex AMS and IO subsystems
Design, synthesis, and verification of Verilog/SystemVerilog RTL
Analyze, debug, and resolve Lint and CDC issues in the design
Ensure design convergence to timing closure utilizing RTL optimization strategies
Conduct formal verification of design with Synopsys Formality / Cadence Conformal
Generate timing constraints for Synthesis and STA at the block-level and SoC top-level
Drive comprehensive test plans to ensure quality of design
Collaborate with cross-functional teams

Requirements

MS +10 years of relevant industry experience
Experience with digital implementation flow from RTL synthesis to timing closure
Deep understanding of timing analysis with Primetime flow and generation of Liberty models
Experience with Tessent tool for DFT insertion and verification
Proficient with Perl, Python and Tcl scripting
Strong problem solving skills with attention to detail
Must be self-motivated and able to work effectively across internal and external engineering teams

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

VerilogSystemVerilogRTL synthesistiming analysisLint debuggingCDC resolutionformal verificationtiming constraintsDFT insertionscripting

Soft Skills

problem solvingattention to detailself-motivatedcollaboration