Senior ASIC DV Engineer
Broadcom
full-time
Posted on:
Location Type: Office
Location: San Jose • California • United States
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Salary
💰 $141,300 - $226,000 per year
Job Level
About the role
- Contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips
- Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs
- Developing test plans and coverage metrics from specifications and writing block and chip-level tests
- Debugging RTL and Gate simulations and work with design engineers to verify fixes
- Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC
- Replicating silicon bugs in simulation environments and validating fixes or SW workarounds
- Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up
- Evaluating latest verification methodologies and developing scripts etc. to automate verification flows
Requirements
- Bachelors and 12+ years of related experience
- or Masters degree and 10+ years of related experience
- or PhD and 7+ years of related experience
- MS or PhD is preferred
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave and vacation time
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SOC developmentUVMconstrained random techniquestest planscoverage metricsRTL debuggingGate simulationsFPGA validationASIC validationverification methodologies