Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs
Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification
Understand Verilog-AMS modeling language
Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model

Requirements

Bachelor's degree
8+ years of related experience
Good knowledge of SystemVerilog UDT/UDR nettype
Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter
Understand good coding of RTL of digital design and testbench creation
Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs)
Hands-on skills in scripting languages (TCL/Perl/Python)
Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec

Benefits

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills

Digital-Mixed Signal modelingVerilog-AMSSystemVerilog UDTSystemVerilog UDRRTL codingtestbench creationanalog circuit designscripting languagesAI toolschip verification

Certifications

Bachelor's degree