PLL IC Design Engineer

BLUE ORIGIN

IC Design Engineer responsible for developing PLL circuits for satellite communications at Blue Origin. Collaborating with architects and engineers to optimize performance in advanced CMOS technologies.

Posted 6/20/2026full-timeSan Diego • California, Washington • 🇺🇸 United StatesSeniorLead💰 $230,398 - $322,556 per yearWebsite

About the role

Key responsibilities & impact

Owning the system and circuit design of PLLs and clock distribution circuits in advanced CMOS technologies, focusing on performance optimization and trade-off analysis (phase noise / jitter, power, etc.).
Utilizing full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.
Collaborating with RF and SOC system architects and chip leads to define requirements for PLLs and their sub-blocks based on system specifications.
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.
Working closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.
Investigating and implementing fundamental analog building blocks to enhance overall circuit performance.
Mentoring junior engineers for best design practices in analog domain.

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, or related technical discipline
7+ years of experience in the design and development of fractional-N PLLs, DLLs, and their sub-circuits in FinFET CMOS nodes such as 7n or more advanced.
Extensive experience in the design of PLL building blocks such as VCOs, high-speed integer and frac-N pre-scalers, PFDs, charge-pumps, etc.
Experience with clock domain synchronization techniques within systems involving multiple PLLs and/or clock domains.
Experience with clock distribution circuit design techniques and optimization, including clock trees, frequency multipliers and dividers, CML buffers, inductive peaking, etc.
Full proficiency in mixed-mode modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.
Extensive experience in PLL silicon characterization and debugging.
Proficiency in the design of fundamental analog/RF building blocks, including amplifiers, filters, clock buffers, and bias generators.
Must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

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Hard Skills & Tools

system designcircuit designPLL designfractional-N PLLsDLLsVCOshigh-speed pre-scalersPFDscharge-pumpsanalog building blocks

Soft Skills

collaborationmentoringperformance optimizationtrade-off analysiscommunication

Certifications

Bachelor's degree in Electrical Engineering