Senior ASIC Design Verification Engineer

BLUE ORIGIN

ASIC Verification Engineer leading complex digital subsystem verification for next-generation Satellite communication ASICs. Collaborating with multi-functional teams to ensure robust, high-quality silicon.

Posted 6/17/2026full-timeLos Angeles • California, Texas, Washington • 🇺🇸 United StatesSenior💰 $230,398 - $322,556 per yearWebsite

About the role

Key responsibilities & impact

Lead verification planning and execution for complex blocks or subsystems.
Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions.
Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals.
Drive functional coverage closure, regression health, and verification signoff readiness.
Identify verification gaps, corner cases, and high-risk scenarios early in the development cycle.
Collaborate closely with design, systems, DFT, firmware, and physical design teams.
Review testbench architecture, stimulus quality, and debug methodologies for technical excellence.
Mentor junior engineers in verification standard processes.
Support bring-up, emulation, prototyping, and post-silicon debug activities as needed.

Requirements

What you’ll need

BS or MS in Electrical Engineering, Computer Engineering, or related field
8+ years of ASIC/SoC verification experience
Deep hands-on expertise in System Verilog and UVM
Strong understanding of verification planning, assertions, and coverage closure
Experience verifying complex digital control and datapath logic
Proven debugging capability across RTL, testbench, and system interactions
Ability to work effectively across multidisciplinary engineering teams.
Background in Space based communications, wireless communications, or modem/baseband hardware (preferred)
Experience verifying LDPC/BCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines (preferred)
Familiarity with formal verification tools and methodologies (preferred)
Experience with low-power verification, CDC/RDC verification, or reset-domain behavior (preferred)
Knowledge of high-speed interface verification and hardware/software interactions (preferred)

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion.

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

System VerilogUVMverification planningassertionscoverage closuredebuggingASIC verificationSoC verificationlow-power verificationformal verification

Soft Skills

collaborationmentoringproblem-solvingcommunicationteamwork