Principal ASIC Design Verification Engineer

BLUE ORIGIN

. Define end-to-end verification strategy for large Satellite communication ASIC or SoC programs.

Posted 5/2/2026full-timeCentral Texas • California, Texas, Washington • 🇺🇸 United StatesLead💰 $230,773 - $323,081 per yearWebsite

About the role

Key responsibilities & impact

Define end-to-end verification strategy for large Satellite communication ASIC or SoC programs.
Establish verification methodologies, infrastructure, and signoff criteria across block, subsystem, and SoC levels.
Lead verification planning for complex communication functions such as modem pipelines, FEC engines, digital beamforming, packet processing, and control fabrics.
Drive alignment among design, architecture, systems, firmware, and validation teams.
Evaluate verification completeness through coverage, assertions, formal analysis, emulation, and silicon correlation.
Resolve critical technical issues and direct root-cause analysis for the most complex functional failures.
Guide development of reusable VIP, reference models, and regression automation frameworks.
Mentor technical leaders and raise the overall verification maturity of the organization.
Influence future verification roadmap, tool strategy, and reuse models.

Requirements

What you’ll need

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
12+ years of ASIC/SoC verification experience.
Expert-level knowledge of System Verilog, UVM, assertions, and verification signoff methodology.
Proven success leading verification for complex chips or multiple tape-outs.
Strong understanding of communication signal-processing hardware and system-level integration.
Excellent technical leadership and cross-organizational communication skills.
Deep expertise in Space based communications, digital modems, phased-array processing, or payload processing. (Preferred)
Experience with formal property verification, emulation, and performance validation. (Preferred)
Familiarity with fault tolerance, mission-critical reliability, or radiation-aware verification considerations. (Preferred)
Experience with architectural modeling and verification planning for hardware/software partitioned systems. (Preferred)
Strong record of technical innovation and process improvement. (Preferred)

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

ASIC verificationSoC verificationSystem VerilogUVMassertionsverification signoff methodologyformal property verificationemulationperformance validationarchitectural modeling

Soft Skills

technical leadershipcross-organizational communicationmentoringproblem-solvingroot-cause analysisprocess improvementinfluencingcollaborationstrategic planningevaluation

Certifications

BS in Electrical EngineeringMS in Electrical EngineeringPhD in Electrical EngineeringBS in Computer EngineeringMS in Computer EngineeringPhD in Computer Engineering