Principal Silicon Physical Design, Layout Engineer

BLUE ORIGIN

. Execute physical design and layout of ASICs that integrate both analog and digital processing .

Posted 5/2/2026full-timeCalifornia, Texas, Washington • 🇺🇸 United StatesLead💰 $230,773 - $323,081 per yearWebsite

About the role

Key responsibilities & impact

Execute physical design and layout of ASICs that integrate both analog and digital processing
Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs
Develop ASICs that meet the stringent standards of space qualification, ensuring high performance and efficiency
Perform timing closure, signal integrity analysis, and physical verification (DRC/LVS/ERC)
Implement advanced RF processing technologies that support missions with reduced size, weight, and power (SWaP)
Optimize layouts for radiation tolerance and reliability in the space environment
Collaborate with front-end designers to ensure design intent is preserved through implementation
Perform static timing analysis and address timing violations
Utilize data analytics to optimize ASIC performance and drive innovation
Work with semiconductor foundries to ensure manufacturability and yield optimization
Implement design for test (DFT) structures and methodologies
Document physical design processes, methodologies, and results
Support post-silicon validation and debug activities

Requirements

What you’ll need

B.S. degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in physical design and layout of ASICs
Demonstrated expertise in digital and analog layout techniques
Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor)
Knowledge of semiconductor fabrication processes and design rules
Understanding of timing closure and signal integrity challenges
Experience with power analysis and optimization techniques
Preferred Qualifications: Experience with mixed-signal or RF layout techniques
Knowledge of radiation-hardened design methodologies
Experience with advanced process nodes (16nm and below)
Background in high-speed digital design (>1GHz)
Experience with 3D packaging or chiplet technologies
Understanding of thermal considerations in ASIC design
Familiarity with space qualification requirements for electronic components
Experience with low-power design techniques for battery or solar-powered systems.

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
Employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.

ATS Keywords

✓ Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

physical designlayout of ASICsfloor planningpower distributionclock tree synthesisroutingtiming closuresignal integrity analysisstatic timing analysisdesign for test (DFT)

Soft Skills

collaborationdocumentationinnovation