Senior ASIC Design Engineer
BLUE ORIGIN
full-time
Posted on:
Location Type: Hybrid
Location: Los Angeles • California • Washington • United States
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Salary
💰 $197,529 - $276,539 per year
Job Level
About the role
- Lead the design and delivery of complex ASIC IP or subsystems from specification through RTL release.
- Define microarchitecture for high-speed, power-efficient digital signal-processing and control logic.
- Drive IP or subsystem trade studies involving throughput, latency, area, power, reliability, and schedule.
- Collaborate with systems, algorithm, and architecture teams to translate communication requirements into hardware implementations.
- Partner with verification, DFT, physical design, and firmware teams to ensure successful integration and tape-out readiness.
- Review RTL, test plans, and implementation results to maintain high design quality.
- Identify and mitigate technical risks early in the development cycle.
- Mentor junior engineers and help establish standard processes in coding, review, and debug.
- Support post-silicon bring-up and root-cause analysis of lab or field issues.
Requirements
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 5–8+ years of ASIC digital design experience
- Proven experience owning large blocks or subsystems in ASIC or FPGA development
- Strong expertise in System Verilog/Verilog RTL design and debug
- Working knowledge of synthesis, STA concepts, CDC/RDC, and integration flows
- Experience balancing PPA tradeoffs in production-quality designs
- Demonstrated ability to work across multidisciplinary teams
Benefits
- Medical, dental, vision, basic and supplemental life insurance
- Paid parental leave
- Short and long-term disability
- 401(k) with a company match of up to 5%
- Education Support Program
- Up to four (4) weeks paid time off per year based on weekly scheduled hours
- Up to 14 company-paid holidays
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
ASIC designdigital signal processingmicroarchitectureSystem VerilogVerilog RTL designsynthesisstatic timing analysisclock domain crossingreliability analysispower efficiency
Soft Skills
mentoringcollaborationrisk managementproblem-solvingcommunication