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Radio FPGA Engineer III – Lunar Permanence
BLUE ORIGIN. Design and simulation of end-to-end systems to meet required performance specification such as range and signal-to-noise ratio .
Posted 3/27/2026full-timeDenver • Colorado, Washington • 🇺🇸 United StatesMid-LevelSenior💰 $119,814 - $167,738 per yearWebsite
Tech Stack
Tools & technologiesDACFlash
About the role
Key responsibilities & impact- Design and simulation of end-to-end systems to meet required performance specification such as range and signal-to-noise ratio
- Design and validate signal processing algorithm for applications of detection, tracking, RF calibration, parameter estimation
- Support Matlab/Simulink Code generation for signal processing and filtering
- Analysis of algorithmic computational complexity and hardware resource needs (FPGA fabric, memory/IO bandwidth, etc.)
- Signal-to-Noise/Clutter Ratio, Signal Sensitivity, RF nonlinearity calibration
- Work with hardware engineers to drive device selection : FPGA, ADC/DAC, DDR3/4, NOR flash, etc.
- Support HW bring-up and work alongside EE engineers to support design verification RTL logic implementation and FPGA prototyping
Requirements
What you’ll need- B.S. in Electrical Engineering or a related field with 5+ years of DSP experiences
- Experience in developing and implementing DSP algorithm on FPGA and/or embedded processor
- Experience in simulating an end-to-end system to meet required performance specifications, such as link budget
- Proficient with Matlab/Simulink, or equivalent modeling environment
- Experience in designing, choosing, and optimizing DSP algorithms for radar or other relevant sensors
- Proficient with IEEE 802.3, XAUI, PCIe, JESD204B/C, I2C, SPI interfaces
- Proficient in writing RTL using Verilog/SystemVerilog/VHDL (SystemVerilog desired)
- Strong understanding of FPGA design concepts, CDC, constraint definition, STA, and timing closure
- Proficient with FPGA development tools such as Xilinx Vivado, Intel Quartus
- Proficient with ModelSim/QuestaSim or equivalent simulators
- Experience in writing testbenches utilizing techniques such as UVM/OVM, SV Assertion, and/or functional/code coverage analysis
Benefits
Comp & perks- Medical, dental, vision, basic and supplemental life insurance
- Paid parental leave
- Short and long-term disability
- 401(k) with a company match of up to 5%
- Education Support Program
- Up to four (4) weeks of paid time off per year
- Up to 14 company-paid holidays
ATS Keywords
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Hard Skills & Tools
signal processingDSP algorithm developmentFPGA designRTL codingMatlabSimulinkVerilogSystemVerilogVHDLtestbench writing