Research, design, and evaluate CPU microarchitectural components (pipelines, fetch/decode, branch prediction, caches, memory hierarchy, OoO/rename/issue, interconnects, SIMD/vector/matrix units). Analyze and optimize PPA trade-offs for AI, HPC, and cloud workloads.
Build and validate performance/functional models, run simulations, and correlate results to RTL to guide architectural decisions.
Develop and evaluate architectural extensions within RISC-V; assess their performance, programmability, and toolchain compatibility.
Propose, model, and prototype new mechanisms to improve efficiency, scalability, and performance.
Work closely with hardware, compiler, and system teams to align roadmaps and enable new capabilities. Stay ahead of trends in CPU, memory, interconnect, and AI-adjacent architectures.
Requirements
MS/PhD in CE/EE/CS (or related field) with focus on CPU architecture or microarchitecture.
Deep expertise in CPU design (pipelines, memory systems, coherence, SIMD/vector/matrix units), PPA optimisation, and ISA extensions (RISC-V, ARM, x86).
Skilled in performance modeling and simulation (e.g., gem5, ChampSim, Sniper, QEMU), cycle-accurate and trace-driven analysis, and correlation to RTL.
Experienced in benchmarking and workload characterisation (SPEC, MLPerf, or internal suites).
Proficient in RTL design and validation (Verilog/SystemVerilog/Chisel), including simulation, synthesis, and FPGA/emulation bring-up.
Knowledge of compiler/toolchain integration, low-level software (C/C++/assembly), Linux kernel/driver development, and performance tuning for ISA features.
Strong analytical, collaborative, and communication skills with proven ability to drive architectural proposals from concept to validation.
Fluent in English
Able to work from one of our European offices or remotely, preferably based in Bavaria (Munich), Belgium, or Italy.
Benefits
pension plan
extensive employee insurances
option to get company shares
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
CPU microarchitecturePPA optimizationRISC-Vperformance modelingsimulationRTL designVerilogSystemVerilogCC++