ASIC Verification Engineer
Atos
full-time
Posted on:
Location Type: Office
Location: Bangalore • India
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About the role
- Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
- Write and perform the test plan in close cooperation with the logical design team.
- Develop coverage models and verification environments using UVM-SystemVerilog / C++.
- Write, maintain and publish the verification specification.
- Monitor, analyze and debug simulation errors.
- Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
- Produce a maintainable and reusable code across projects.
Requirements
- 3-5 years of experience
- Bachelor’s degree (BE/B.Tech) or Master’s degree (ME/M.Tech)
- Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages
- Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergroup / SVA)
- Knowledge of simulation tools and coverage database visualization tools
Benefits
- 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave.
- Benefit Plans (Insurance) – Medical & Life & Accidental & EDLI
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
UVMSystemVerilogC++Constraint-Random verificationCoverage-Driven verificationsimulation error debuggingverification specification writingcoverage modelsverification environmentssimulation coverage analysis
Certifications
Bachelor’s degreeMaster’s degree