Astera Labs

Systems Engineer

• Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads
• Design and integrate PCIe-based subsystems including GPU, accelerator, and high-speed I/O components leveraging PCIe Gen5/6 technologies
• Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads
• Architect and optimize high-speed Ethernet networking interfaces (25G/100G/400G+) within platform designs
• Drive system-level integration across compute, networking, and storage subsystems
• Develop and validate FPGA-based solutions for system control, monitoring, and acceleration
• Lead system bring-up, debug, and validation in lab environments
• Troubleshoot complex hardware and performance issues across high-speed signaling, power, thermal, and interconnect domains
• Define and implement platform management solutions including BMC integration, telemetry, health monitoring, and system-level diagnostics
• Collaborate with cross-functional teams spanning hardware, firmware, BIOS, and OS to ensure seamless platform integration
• Partner with silicon vendors, OEMs, and hyperscalers on custom platform development aligned with Astera Labs' connectivity ecosystem
• Drive performance optimization across PCIe topology, accelerator interconnects, and memory subsystems.

Senior Principal Hardware Systems Engineer

Architect

• Lead end-to-end system architecture and design for server platforms including x86 multi-socket and accelerator-based systems
• Define and maintain multi-platform design standards and architectures that scale across product lines
• Drive hardware platform development including board design, system bring-up, and validation
• Oversee system-level integration across compute, storage, and interconnect subsystems — including PCIe Gen5/6 and high-speed fabric connectivity
• Lead FPGA architecture and development including simulation, synthesis, validation, and common framework definition
• Drive signal integrity analysis, functional validation, and defect resolution across complex hardware systems
• Own hardware debug and bring-up in lab environments, ensuring seamless integration with firmware and software stacks
• Provide technical leadership and mentorship to distributed engineering teams across hardware, firmware, and platform disciplines
• Coordinate cross-functional activities to ensure alignment between hardware design, firmware integration, and system validation
• Collaborate with customers and stakeholders on custom system solutions, technical briefings, and field issue resolution
• Partner with silicon vendors, OEMs, and hyperscalers to drive platform innovation aligned with Astera Labs' connectivity ecosystem

Senior Principal Hardware System Architect

LLM Engineer

• Lead and manage global AI, Storage, and Networking hardware design programs, ensuring on-time delivery, scope control, and budget adherence
• Drive program governance, risk management, and execution excellence across all phases of product development
• Provide regular program updates, risk assessments, and financial reporting to executive leadership through structured reviews (e.g., Leadership Program Reviews)
• Oversee the successful launch of complex hardware platforms, including AI GPU-based systems
• Manage high-priority, resource-constrained programs while maintaining quality and schedule commitments
• Enable innovation in next-generation AI infrastructure and high-performance computing platforms
• Lead end-to-end program management for UALink / PCIe Gen6 switch tray development supporting rack-scale AI platforms and GPU clusters
• Coordinate design, validation, and manufacturing readiness of switch trays across EVT, DVT, and PVT phases
• Drive integration of switch silicon, retimer cards, cabling, and system-level connectivity within full rack-scale architectures
• Collaborate with ODMs and partners to align on design specifications, cost models, and development schedules
• Manage technical trade-offs across performance, signal integrity, power delivery, thermals, and scalability for high-density GPU deployments
• Partner with Tier-1 customers to deliver Joint Design Manufacturing (JDM) programs
• Ensure alignment with customer-specific requirements in design, supply chain, and quality
• Build strong customer relationships and act as a trusted advisor throughout the product lifecycle
• Lead globally distributed teams across engineering (HW/SW), supply chain, manufacturing, and quality organizations
• Coordinate teams across multiple regions (e.g., North America and Asia) to drive seamless execution
• Guide programs through EVT, DVT, and PPVT phases, ensuring technical validation across electrical, thermal, power, signal integrity, and mechanical domains

Principal AI Infrastructure – Hardware Program Management

Hardware Engineer

• Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems
• Drive adoption of PCIe/UAlink-based fabrics for disaggregated compute, memory, and accelerator scalability
• Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads
• Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem
• Lead system architecture and design for high-performance compute platforms optimized for AI and accelerator-driven workloads
• Define and implement GPU-enabled server platforms for AI training, inference, and HPC workloads
• Define the technical vision and multi-year product roadmap for AI infrastructure platforms.

Distinguished Engineer – System & Rack Hardware Architecture

• Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems
• Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability
• Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads
• Lead integration of connectivity solutions — retimers, switches, and fabric controllers — aligned with Astera Labs' product ecosystem
• Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks
• Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms
• Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms
• Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads
• Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies
• Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads
• Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers
• Influence industry standards across OpenBMC, Redfish, OCP, and related consortia
• Mentor senior engineers and grow deep technical bench strength across the organization
• Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation.

Distinguished Engineer – Server Firmware, System Architecture

Application Engineer

• Serve as the primary technical point of contact for strategic customers, providing deep application support for Aries, Scorpio, and Leo product families
• Drive board design reviews, schematic reviews, and system-level debug sessions with customer hardware and system development teams
• Deliver technical presentations, training sessions, and product demonstrations tailored to customer architectures and use cases
• Lead hands-on debug of PCIe, Ethernet, and CXL/DDR memory connectivity issues in customer server and rack-scale platforms
• Collaborate with internal silicon, firmware, and applications engineering teams to resolve field issues and drive root cause analysis
• Develop and maintain application notes, reference designs, and technical collateral based on field learnings
• Capture and communicate customer requirements, competitive insights, and system architecture trends to product management and engineering
• Represent the voice of the customer in internal roadmap discussions, helping shape next-generation connectivity solutions
• Identify new use cases and expansion opportunities within existing accounts.

Senior Principal Hardware Systems Engineer

Senior Principal Hardware System Architect

Principal AI Infrastructure – Hardware Program Management

Distinguished Engineer – System & Rack Hardware Architecture

Distinguished Engineer – Server Firmware, System Architecture

Lead Field Application Engineer