Senior Design Verification Engineer

Arrow Components

Senior Design Verification Engineer at eInfochips building scalable verification environments using UVM and SystemVerilog. Collaborating with teams to ensure functional and code coverage metrics are met.

Posted 6/14/2026full-timeMinneapolis • Minnesota • 🇺🇸 United StatesSeniorWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Build scalable verification environments using UVM and SystemVerilog.
Create detailed verification plans from architectural specifications.
Write, run, and debug constrained-random tests and directed tests.
Define, measure, and close functional and code coverage metrics.
Run gate-level simulations to verify power-up and timing states.
Develop scripts to automate regression runs and triage failures.

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Strong proficiency in SystemVerilog and scripting (Python, Perl, or Tcl).
Hands-on experience with UVM (Universal Verification Methodology)
Experience with industry-standard simulators Cadence Xcelium preferred, but experience with Synopsys VCS, or Siemens Questa will translate
Deep understanding of constrained-random verification, assertions (SVA), and functional coverage.
Knowledge of common protocols like AMBA (AXI/AHB/APB)
Experience with formal verification tools and methodologies (Preferred Qualification)
Background in power-aware verification using UPF/CPF.
Experience verifying custom ARM or DSP processor cores.
Familiarity with emulation platforms like Palladium.
Experience with: MMU verification SRAM/ memory subsystem verification
Nice-to-have: DSP verification experience Modeling (RNM / behavioral models)

Benefits

Comp & perks

Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities
And more!

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SystemVerilogUVMPythonPerlTclconstrained-random verificationfunctional coveragepower-aware verificationformal verificationDSP verification