Senior DFT Engineer

Sr DFT Engineer designing and implementing DFT processes for eInfochips, collaborating closely with test engineers and physical design teams.

Posted 6/12/2026full-timeSan Jose • California • 🇺🇸 United StatesSeniorWebsite

Key responsibilities & impact

Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level.
Verify test patterns using gate-level simulations.
Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.
Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing.

What you’ll need

Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST.
Proven experience in developing DFT specifications and architectures for complex designs.
Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more.
Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification.
Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes.
Efficient scripting skills using TCL for automating tasks and developing custom flows.

Comp & perks

ATS Keywords

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Hard Skills & Tools

DFTATPGMBISTTCLgate-level simulationscoverage analysisdebuggingvector generationsilicon debugDFT specifications

Soft Skills

collaborationproblem-solvingdata analysis