Principal Digital Design Engineer – ASIC

Analog Devices

Principal Digital Design Engineer driving technical strategy and overseeing complex digital systems for Analog Devices. Leading ASIC architecture and defining technology roadmaps in a collaborative environment.

Posted 6/22/2026full-timeSomerset • Massachusetts, New Jersey • 🇺🇸 United StatesLead💰 $159,638 - $239,457 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs)
Define product and technology roadmaps
Lead ASIC architecture for mission-critical projects
Serve as a technical authority within the organization
Develop and maintain system-level models (e.g., in SystemVerilog, or MATLAB)
Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or subsystems
Collaborate closely with multi location teams during architecture, design, evaluation, and release phases
Lead design reviews, participate in specification, and ensure alignment with broader project goals
Perform RTL coding (Verilog and SystemVerilog), synthesis, and lint/CDC analysis; drive designs to timing closure and area/power targets
Develop and execute verification plans in collaboration with DV
Analyze and resolve design, timing, and functional issues across the full digital development flow
Contribute to top-level integration
Mentor and guide junior engineers
Author and maintain clear documentation, user guides, and design collateral
Stay current with industry trends and identify opportunities for process or technology improvement
Perform silicon lab evaluation and debug
Use Python applications to develop tests on evaluation platforms

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in digital design for ASIC/SoC, with track record of successful tapeouts
Strong understanding of ASIC Design flow
Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools
Experience with modeling and scripting (Matlab, TCL, Python) for design automation
Strong understanding of digital design flows, timing analysis, and constraints
Experience collaborating across functions (DV, PD, systems, analog/mixed-signal)

Benefits

Comp & perks

Medical, vision, and dental coverage
401k
Paid vacation
Holidays
Sick time
Discretionary performance-based bonus

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

System on Chips (SoCs)ASIC architectureSystemVerilogRTL designVeriloglogic synthesisdigital verification methodologiestiming analysisdesign automationPython

Soft Skills

technical authoritycollaborationleadershipmentoringdocumentationproblem-solvinginnovationcommunicationevaluationguidance